1. Field of the Invention
The present invention relates to a structure of a memory device and a fabrication method thereof. More particularly, the present invention relates to a structure of buried bit line of a memory device and a fabrication method thereof.
2. Description of Related Art
Memory device, by nature, is a semiconductor device used to store information and data. The storage of digital information is in unit of bit. Information is stored in a cell in the memory device. The specific location of each memory cell is known as an address. In other words, the memory cells in a memory device are arranged in an array, wherein a specific row and column constitutes a specified memory cell address. The memory cells on each row or each column are connected with a common conductive line.
Referring to FIG. 1, FIG. 1 is a schematic, cross-sectional view of a structure of a memory cell device according to the prior art.
Referring to FIG. 1, a conventional memory device comprises a substrate 10, a buried bit line 12, a gate oxide layer 16, an insulation structure 14 and a word line 18. The buried bit line 12 is disposed in the substrate, while the word line 18 extends above and across the buried bit line 12. Further, the gate oxide layer 16 is disposed on a surface of the substrate 10 to electrically isolate the word line 18 and the substrate 10. The insulation structure 14 is disposed above the buried bit line 12 to electrically isolate the word line 18 and the buried bit line 14.
Accompanying the increase of circuit integration and the miniaturization of device dimension, the linewidth of the buried drain region is also being scaled down. A narrower linewidth, however, would lead to its resistance to increase. Consequently, the current flow of the memory device is reduced and bit line loading would become too high. If the junction depth of the buried drain region is increased to resolve the problem of raised resistance at the linewidith, not only is the short channel effect generated, the problem of junction leakage also occurs. If a high concentration of dopants is used to form a shallow junction of the bit line to obviate the short channel effect and the junction leakage problem due to a deep junction, the overloading problem of the bit line remains unresolved because of the limitation of the solid-phase solubility. Further, in a conventional memory device, a bit line contact is required for every 32 bit lines or 64 bit lines to control the memory device. The formation of a bit line contact, however, is limited by the integration of the device. Lower the number of the bit line contact in order to increase the integration of the device is thus very important.
Accordingly, the present invention provides a structure of a buried bit line of a memory device and a fabrication method thereof, wherein the bit line resistance is reduced.
The present invention also provides a structure of a buried bit line of a memory device and a fabrication method thereof, wherein the generation of the short channel effect and the junction leakage problem are prevented.
The present invention further provides a structure of a memory device and a fabrication method thereof, wherein the number of the bit line contacts in the device is reduced to increase the integration of the device.
In accordance to the present invention, a structure of a memory device is provided, the structure comprises a substrate, a deep doped region and a shallow doped region. The shallow doped region is disposed in the substrate while the deep doped region is disposed in the substrate under a part of the shallow doped region. The shallow doped region and the deep doped region together serve as a buried bit line of the memory device. In the present invention, the dopant concentrations in the deep doped region and in the shallow doped region are about the same. The dopant concentrations in the shallow doped region and the deep doped region are about 1021/cm3 to 1022/cm3.
The present invention provides a fabrication method for a memory device. This method comprises forming a patterned mask layer on a substrate, wherein this mask layer is a photoresist layer, a polysilicon layer or a dielectric layer (for example, silicon nitride or silicon oxide type of dielectric material). Thereafter, using the mask layer as an ion implantation mask, a first ion implantation process is performed to form a shallow doped region in the substrate not covered by the mask layer. A linear layer is then formed on the surface of the mask layer, wherein the liner layer is formed by, for example, plasma enhanced chemical vapor deposition and the liner layer is, for example, a polymer liner layer. A point that is worth noting is that if the liner layer formed on the surface of the mask layer is a polymer layer, the liner layer can be reworked even deviation occurs in the critical dimension of the liner layer. A second ion implantation process is performed to form a deep doped region in the substrate not covered by the liner layer and the mask layer, using the liner layer and the mask layer as an implantation mask, wherein the shallow doped region and the deep doped region together form a bit line of a memory device. The mask layer and the liner layer are then removed, followed by forming a gate oxide layer on the surface of the substrate and a gate on the gate oxide layer.
The present invention provides a memory device, the device comprises a substrate, a gate, a gate oxide layer, a deep doped region and a shallow doped region. The gate is disposed on a part of the substrate while the gate oxide layer is disposed between the substrate and the gate. The shallow doped region is disposed in the substrate beside both sides of the gate while the deep doped region is disposed in the substrate under a part of the shallow doped region. The shallow doped region and the deep doped region together serve as a buried bit line of a memory device. In this aspect of the present invention, the dopant concentrations in both the deep doped region and the shallow doped region are about 1021/cm3 to 1022/cm3.
The present invention provides a fabrication method for a memory device. This method comprises forming a patterned mask layer on a substrate, wherein this mask layer is a photoresist layer, a polysilicon layer or a dielectric layer (for example, silicon nitride or silicon oxide type of dielectric material). Thereafter, using the mask layer as an ion implantation mask, a first ion implantation process is performed to form a shallow doped region in the substrate not covered by the mask layer. A linear layer is then formed on the surface of the mask layer, wherein the liner layer is formed by, for example, plasma enhanced chemical vapor deposition and the liner layer is, for example, a high molecular weight liner layer. A point that is worth noting is that if the liner layer formed on the surface of the mask layer is a high molecular material layer, the liner layer can be reworked even deviation occurs in the critical dimension of the liner layer. A second ion implantation process is performed to form a deep doped region in the substrate not covered by the liner layer and the mask layer, using the liner layer and the mask layer as an implantation mask, wherein the shallow doped region and the deep doped region together form a bit line of a memory device. The mask layer and the liner layer are then removed, followed by forming a gate oxide layer on the surface of the substrate and a gate on the gate oxide layer.
Accordingly, the buried bit line is formed with the shallow doped region and the deep doped region, the resistance of the bit line of the memory device is thus lowered.
The junction of the shallow doped region of the buried bit line of the present invention can be made shallower. The problems of the short channel effect and leakage current are prevented to raise the reliability of the device. Moreover, the resistance created in the shallow doped region is also being compensated. Therefore, forming a narrower deep doped region under shallow doped region, the resistance of the entire buried bit line is lower.
In accordance to the memory device of the present invention and the fabrication method thereof, since the resistance of the bit line is effectively lowered, the voltage of the bit line can be lowered to reduce the number of the bit line contacts in the device to increase the integration of the device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.